1. Field of the Invention
This invention is generally related to the field of semiconductor devices, and, more particularly, to various methods of forming a P-well in an integrated circuit device.
2. Description of the Related Art
In some environments, modern integrated circuit devices are designed to operate in high voltage environments, e.g., 80-250 volts. One illustrative example of such a high voltage application would be integrated circuits on subscriber line interface cards (SLIC) which are in widespread use in modern telecommunication systems. In some cases, the circuits on such devices are comprised of complementary bipolar transistors, i.e., NPN and PNP bi-polar transistors.
Typically, such bi-polar transistors are formed above a silicon-on-insulator (SOI) structure. Initially, the process involves forming a relatively thick layer of epitaxial silicon, e.g., 12-30 microns, above the active layer of the SOI structure. In forming the PNP bi-polar transistor, a P-well must be formed in the epitaxial layer of silicon. Traditionally, in forming such a P-well structure, two ion implantation processes have been performed. The first ion implantation process is performed using aluminum as a dopant material, whereas the second ion implantation process is performed using boron as a dopant material. Aluminum is employed in such structures due to its increased diffusivity characteristics as compared to, for example, boron. Such increased diffusivity is necessary such that the dopant material extends throughout the relatively thick epitaxial silicon layer. More specifically, aluminum is employed in forming a P-well to ensure that the dopant reaches the P+ buried layer formed in the active layer of the SOI structure.
However, the use of the aluminum dopant material has several drawbacks. For example, the use of aluminum leads to increased process variability in parameters such as breakdown voltage, early voltage and quasi saturation. Moreover, the use of a metal such as aluminum can lead to increased leakage currents as the metallic dopant atoms occupy defect sites within the epitaxial silicon layer. The use of aluminum, or other metallic dopants, may also increase the risk of contaminating other areas of the integrated circuit device with aluminum. Thus, there is a need for an improved methodology of forming P-well regions in high voltage devices having relatively thick layers of epitaxial silicon without using aluminum as the dopant material.
The present invention is directed to various methods that may solve, or at least reduce, some or all of the aforementioned problems.